Blaine C. Readler
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A Concise Introduction for FPGA Design.
Verilog by Example cover                                 ISBN: 978-0-9834973-0-1
                                124 Pages, 6" x 9"- $19.95
                                Published by Full Arc Press

A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions.
What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.

Sample a chapter (right-click to download PDF)

Verilog TOC
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Available June, 2011 at book stores such as Barnes and Nobles and Borders, & online.

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Sample code files: bus_breakout.v
bus_sigs.v
clock_buffer.v
dflop_en_clr.v
dflop_n_reset.v
full_dp_mem.v
intermed_wire.v
modular_1.v
modular_2.v
sim_sample.v
simple_dflop.v
simple_dp_mem.v
simple_in_n_out.v
single_port_mem.v
srflop_n_cntr.v
srflop_n_cntr_1.v
standard_mux.v
state_machine_1.v
state_machine_2.v
tb_sim_sample_1.v
tb_sim_sample_2.v