//////////////////////////////////////////
// Sample Design for Simulation

module sim_sample (  clk,
                     reset,
                     dat_in,
                     enable,
                     comp_cnt
                   );          

    input          clk;
    input          reset;
    input  [7:0]   dat_in;
    input          enable;
    output [9:0]   comp_cnt;

    reg [7:0]   dat_in_d1;
    reg [9:0]   comp_cnt;

    // ------ Design implementation -----

    always @( posedge clk or posedge reset )
      begin
        if ( reset )
          begin
            dat_in_d1 <= 8'h00;
            comp_cnt  <= 10'd0;
          end
        else if ( enable )
          begin
            dat_in_d1 <= dat_in;
            if ( dat_in_d1 == dat_in )
              comp_cnt <= comp_cnt + 1;
          end
      end

endmodule