//////////////////////////////////////////
// Simple Testbench Using Embedded, Explicit Vectors

module tb_sim_sample_2 
           (
            // no I/O for the testbench
           );          

   parameter QUANT_VECTORS =  32; //quantity of vector samples

   // input signals to the test module.
   reg        reset;
   reg        sim_clk;
   reg [7:0]  dat_in;
   reg        enable;
   reg [31:0] random_num;

   // output signals from the test module.
   wire [9:0]   comp_cnt;

   // testbench signals.
   integer i;
   integer j;

   // clock periods
   parameter CLK_PERIOD =  10; // 10 ns = 100 MHz.

   // ------ Design implementation -----

   // module under test
   sim_sample  mut
         (  
          .clk      ( sim_clk  ),
          .reset    ( reset    ),
          .dat_in   ( dat_in   ),
          .enable   ( enable   ),
          .comp_cnt ( comp_cnt )
         );          

   // generate clock and reset

   initial sim_clk = 1'b0;

   always #( CLK_PERIOD/2.0 )
     sim_clk = ~sim_clk;     
   
   initial reset   = 1'b1;
   initial i       = 0;
   
   // reset goes inactive after 20 clocks
   always @(posedge sim_clk)
     begin  
       i = i+1;
       if (i == 20)
         #1 reset <= 1'b0;
     end

   // feed stimulus vectors to module under test
   initial
   begin
     dat_in  = 8'b0;
     enable  = 0'b0;
     random_num = $random(1);
     //
     wait (  reset );
     wait ( ~reset );
     @(posedge sim_clk);
     for ( j = 0; j < 20; j = j + 1 )
       begin
         @(posedge sim_clk);
       end
     enable  = 1'b1;
     dat_in  = 8'h00;
     //
     for ( j = 0; j < (QUANT_VECTORS); j = j + 1 )
       begin
         @(posedge sim_clk);
         random_num = $random;
         if ( random_num[2:0] != 3'h0 )
           dat_in = dat_in + 1;
       end
     //
     @(posedge sim_clk);
     enable  = 1'b0;
     //
     forever
       begin
         @(posedge sim_clk)
         enable  = 1'b0;
       end
   end

endmodule